The  VE-HEP  is an ambitious research project that aims to build an open-source based hardware ecosystem for trustworthy electronics and a strong, resilient supply chain as part of the HEP-alliance. The HEP alliance is a consortium of 8 academic and industry partners that are building the next generation of hardware security chips using fully open-source processors and EDA tools.

Hardware trust and secure microelectronics are key requirements that must be fulfilled by an integrated flow from architecture, design to manufacturing platform for an innovative, end-end chip design solution. These devices must function reliably and protect against malfunctions, attacks and accidents during operation. The use of open-source tools and processors are key components and provide differentiated capabilities in building and proving feasibility of this design ecosystem that are not otherwise possible using commercial tools.

OpenROAD is an important application for the generation and support of reliable, open-source hardware for trusted microelectronics. It has recently enabled the PDK support for the BiCMOS process technology created by IHP. OpenROAD is already silicon-proven in building SoCs using the RISC-V processor and its derivatives.

This is a 3 year project funded by the German Federal Ministry of Education and Research (BMBF) aimed at boosting the local semiconductor industry and EWD (Education and Workforce Development) at scale  for Germany.

This blog shares the use of OpenROAD as part of this important strategy for the creation of trusted hardware. Tim Henkes from RheinMain University of Applied Sciences, a part of VE-HEP,  shares his experience using the OpenROAD flow and other open-source tools to design and successfully tape out hardware security blocks.

Leveraging an open-source strategy for trusted microelectronics

The ability to create hardware for trusted microelectronics using open-source tools and hardware has far-reaching applications from military, defense, sensor based systems and personal devices. Trusted microelectronics based applications are especially important to the automotive industry since they are central to the business, brand and reputation.  The use of open-source specifically for design of secure hardware offers unique advantages  and enhances required capabilities:

• Safety and Security
  • Prevention of cyber attacks and unlawful access to vehicle  and passenger information systems
  • Ensuring safety of both passenger and vehicle by preventing attacks on systems like anti-lock braking, collision avoidance, autonomous driving controls etc.

• Reliability
  • Safe and reliable operation of the vehicle throughout its lifecycle under variable environmental conditions of temperature, vibrations , maintenance etc.
• Supply chain resilience
  • Prevent counterfeiting and unauthorized hardware modifications that are dangerous and severely compromise passenger vehicle safety.
• Compliance, Audits and Regulatory standards
  • Guaranteeing compliance, scrutiny and trust for environmental, safety and quality standards
  • Ability to modify processor and hardware architecture for future generation of vehicles and standards.
• Continuous Innovation and Collaboration
  • Open-source tools and flows foster continuous innovation and collaboration among a diverse community of stakeholders: hardware designers, verification engineers, and security experts.

The figure below shows the architecture envisioned by the VE-HEP project to build a reliable and flexible model for trusted microelectronics using open-source design tools and processors.

Image source : HEP alliance

RISC-V and OpenROAD : A trusted flow for HSMs

VE-HEP chose RISC-V as the processor along with OpenROAD to build and study the feasibility of trusted electronics for security using IHP Open PDK.

RISC-V is the natural choice for many applications today due to its open, flexible architecture, ability to design without licensing costs and to rapidly create custom applications for a wide range of technology nodes. The choice of RISC-V with OpenROAD enables a wide range of applications based on IHP’s high performance, 130nm BiCMOS technology: Automotive, IoT, HPC, Medical, Space and Communications and many more.

OpenROAD is the foundational application for SoC design that has been deployed in many silicon-proven designs in > 600+ tapeouts, many of them based on RISC-V microcontrollers.

VE-HEP successfully taped out three designs using OpenROAD in 2023–two of these used OpenLane and the proprietary PDK for the sg13g2 BiCMOS process and produced successfully working chips!. In Dec 2023, Tim switched the flow to use, OpenROAD-flow-scripts (ORFS) for these advantages:

• Fully open-source, Autonomous, No-Human-in-Loop (NHIL)  flow from RTL-GDS
• Compatibility to other open-source and commercial tools
• Support for the IHP PDK
• Ease-of-use and flexibility
• Developer friendly for easy integration and customization
• Rapid turnaround for problem fixes and feature requests

Open-source for Design Hardening and Algorithmic security

Building trustworthy, reproducible and verifiable electronics requires a radically new approach in the design and manufacturing of chip components i.e processor, EDA tools and design and verification methodologies. Chips used for cryptographic operations must ensure algorithmic security during operation without leaking information or becoming vulnerable to hardware attacks.

Open Source design tools allow for code inspection ensuring that the EDA tool itself does not add any trojan to the hardware.

 VE-HEP aims to deliver such a flow created around open-source tools and design components that can be independently customized to suit specific requirements for hardware security  and supply chain sovereignty. To paraphrase their vision for the project : “Hardening the value chain through open-source, trustworthy EDA tools and processors, is to realize essential parts of the entire value chain in the area of ​​development and production of security-relevant chips (hardware security modules) in open source for the first time”.

OpenROAD enables transparency, ownership and hardening of critical cryptographic blocks earlier in the design stage unlike the late stage hardening supported in commercial tools. The OpenROAD based No-Human-in-Loop, RTL-GDS2 flow minimizes human intervention across vulnerable stages of the design. It automatically executes synthesis, DRC-correct PnR with support using the recently enabled open-source IHP PDK. This  makes it possible to prevent hardware trojan attacks, ensure wider transparency and scrutiny across the design and user community and scrutiny.

Hardware security modules (HSMs) store sensitive cryptographic keys and perform secure operations and are often vulnerable to attacks. Side channel attacks exploit unintended design and algorithmic weaknesses that leak information such as power and timing variations that can then be used to infer cryptographic keys and other sensitive information. Prevention of side channel attacks is a key requirement in the design and manufacturing of such hardware security blocks. Another mechanism used by hardware designers  is that of logic locking which allows the insertion of gates to encrypt critical functionality at the RTL level. Logic locking  protects the firmware and cryptographic algorithms implemented in these devices from tampering and reverse-engineering.  A multi-level approach to creating trusted hardware using open-source combines several of these techniques for secure hardware implementation and verification at various design stages thereby enhancing the efficiency and reliability in the design process and reducing costs.

Created HSMs using OpenROAD

“The transition from OpenLane to ORFS was painless. Since both use OpenROAD for large parts of the flow, knowledge acquired from using OpenLane transferred well to ORFS and it was not hard to set up the project build with ORFS. The design (Verilog) was exactly the same for the second and third tapeout.”, says Tim Henkes, describing the transition to ORFS.

The design consists of a RISC-V core, VexRiscv, extended with masked AES as well as a large number multiplication units with 8, 32KiB SRAMs.

The design description uses SpinalHDL that provides useful advantages over conventional RTL descriptions to generate Verilog which was then synthesized and routed using OpenROAD-flow-scripts.

The design source is located here: https://github.com/HEP-Alliance/VE-HEP-HW-SW.

Refer to the ORFS design repository containing all the relevant scripts and design artifacts here: https://github.com/HEP-Alliance/hsm

The design flow consists of a single pass of the NHIL flow in ORFS to generate the layout from the synthesized netlist. The entire design is hardened in a single pass to ensure security in the design stages.

Results

The figure below shows the final GDS layout for the ASIC, including SRAM, the VexRiscv core and the AES block generated in the OpenROAD flow .

Final layout of the ASIC using OpenROAD-flow-scripts

The successfully taped out chip is now being tested at the board level (shown below)

Future vision for Trusted Hardware and supply chain

HEP plans to expand this project to include other key components that strengthen hardware security features that enhance random number generation (TRNG), physical unclonability (PUF)  and protection of chip hardware (eFuses).

“Most importantly we want to add root-of-trust elements like a TRNG, potentially a PUF or eFuses. This will be a large part of the follow-up project we are currently planning. Parts of those efforts concern the tooling, other parts the open PDK.” concludes Tim, as he looks ahead into the near future plans for the project.

This aligns very closely with Germany’s and Europe’s vision for the semiconductor and IT industry.

OpenROAD is a critical enabler and partner in the effort to build trusted electronics and strengthen the hardware supply chain for the semiconductor industry at large.

Reference Links

https://riscv.org/news/2023/10/research-consortium-sets-standards-in-the-field-of-open-source-hardware-open-tools-used-for-a-security-chip/

https://github.com/IHP-GmbH/IHP-Open-PDK

OpenROAD 2023: A Year of Expansion

Goodbye 2023! Hello 2024! Greetings and a Happy New Year from the Precision Innovations team and The OpenROAD Project! Together, we enable innovation, learning, and building chips with lowered barriers of cost, access and expertise. This has been the mission and focus of the OpenROAD project since its inception in the DARPA IDEA program. Thank you to all for your engagement and support, and looking forward to your ongoing contributions!

2023 has been a year of expansion for OpenROAD across many areas: more tapeouts in silicon, more deployments toward education and workforce training, and many important tool enhancements.

Here, we overview important milestones achieved in 2023 and OpenROAD’s plans for 2024.

Tried and Tested for Real-world Applications

OpenROAD has been used for 600+ tapeouts in the Google OpenMPW shuttle program and the Efabless Chipignite program. These include many RISC-V based SoC designs using the OpenROAD-based flows OpenROAD-flow-scripts (ORFS) and OpenLane.  The combined benefits of an open processor ISA, open-source tool integration, and low costs of hardware development have enabled applications – from IoT and sensors to advanced processors and hardware accelerators – across a wide range of functions and technology nodes.

The true test of open-source tools like OpenROAD is how they apply and perform in the real world. A notable application is building hardware security and root-of-trust designs. The following are two example designs using OpenROAD-flow-scripts.

• Root-of-trust.  Mehdi Saligane of the University of Michigan has taped out an Intel 16nm-based SoC containing digital and analog components such as a hardware security block, a processor and a temperature sensor. Specifically, the AES crypto core, the Ibex RISC-V processor, and the temperature sensor were built using OpenROAD and ORFS. Details will follow in a separate blog.
• Trusted microelectronics is an initiative of HEP-Alliance, a group funded by the German government.  The initiative develops trusted security hardware, with strategic use of OpenROAD and other open-source tools, along with a resilient supply chain. Their design consists of a RISC-V core, VexRiscv, extended with masked AES as well as a large-number multiplication unit with eight 32KiB SRAMs. VE-HEP taped out their third update of this design in December 2023. Details will follow in a separate blog. 

Advancing Energy-efficient Processors Using Open-Source Design

Semiconductor startups are starting to leverage open-source tools to realize their designs. With OpenROAD, they gain the benefits of low cost, rapid innovation, transparency and expert support from Precision Innovations.

As one example, Ascenium deployed OpenROAD to develop energy-efficient designs for their General Purpose Processor using a 7nm ASAP7 PDK. Early and rapid microarchitectural exploration is key to their design strategy for development of high-performance, energy-efficient processors with significantly lower costs and greater efficiency than what is possible with commercial EDA tools. The Ascenium team is beginning to see significant progress in the tool usability, stability, and the rich features in the GUI needed to support their differentiated flow and design targets. Øyvind Harboe, VP of Engineering, has been spearheading this effort through an efficient support model with Precision Innovations; he engages proactively in a test-feedback-fix cycle that has been a win-win for all – Ascenium, Precision Innovations, the OpenROAD tool, and the user community at large. Harboe has pioneered a paradigm-shifting approach to designing stringent processor requirements for AI and other advanced applications, enabled by OpenROAD. He remarks: 

“OpenROAD has made a quantum leap in terms of scalability and stability in 2023. We use Bazel with OpenROAD-flow-scripts to enhance the productivity and efficiency of our workflows as we run multiple experiments, continuously integrate and test design changes. We are seeing many improvements overall in terms of the ability to handle large designs with complex macros, constraints that must be managed across the design hierarchy and efficient placement of specialized instances such as large arrays of standard cells. We look forward to enhancements to CTS, hierarchical timing analysis and other features like the automatic macro placement in OpenROAD to get to the superior performance and power targets that our processors deliver over conventional CPU architectures.”

We expect other semiconductor startups to use OpenROAD and gain similar advantages of cost and schedule by combining the best of open-source and commercial EDA tools.

Scaling Education and Workforce Development

OpenROAD is now a leading platform and on-ramp for VLSI education around the world. OpenROAD-based courses and training are the standard for barrier-free and hands-on education and workforce development across many institutions.  Importantly, this supports both growth and stability of semiconductor economies across the entire ecosystem.

Much progress has been made to build scalable and flexible courses, workshops and training programs to serve a wide range of learners, including high schoolers, undergraduates, advanced postgraduates, (Master’s and Ph.D.) and summer interns.

The following are some key highlights:

• University courses
  • https://www.ucsc-extension.edu/certificates/silicon-chip-design-and-semiconductor-engineering/
  • https://www.ucsc-extension.edu/events/asic-design-using-openroad/
  • https://onlinecourses.nptel.ac.in/noc24_ee77/preview

• Education and workforce, faculty development programs
  • https://www.vlsisystemdesign.com/vsdopen2023/
    https://www.vlsisystemdesign.com/basic_courses/
  • Faculty Development Program on Chip Design

• Upskilling at scale
  • Workshop on “OpenROAD for Low-cost ASIC design for Rapid Innovation”

• Hands-on learning: from silicon to tapeout
  • https://ieee-cas.org/universalization-ic-design-cass-unic-cass
  • https://tinytapeout.com/

• Google Summer of Code (GSoC) OpenROAD internships
  • Check out the interesting project accomplishments by our intern, Jack Luar: https://ucsc-ospo.github.io/report/osre23/ucsd/openroad/20231029-luarss/

Austin Rovinski, an original member of the OpenROAD project and ongoing contributor, is an Assistant Professor in the ECE Department at NYU. He has put together an SoC design course as part of a series that uses open-source tools, focusing on the prototyping and evaluation of SoC designs. He notes:

“The goal of this course is to put students in a hardware startup or academic lab context. The key to success in both contexts is prototyping and evaluating solutions that address valuable needs. Therefore, students will learn about how to brainstorm, prototype, and evaluate hardware-based solutions using agile methodologies. FOSS tooling like OpenROAD will be incredibly important for these efforts, as I fully expect students to be able to take their experience from this course and use it to form a startup company if they desire.”

Continuous Development and Innovation

OpenROAD aims to break down barriers to chip design costs and innovation. This calls for continuous improvements to the application and flow capabilities with an ongoing focus on ease-of-use, PPA and access to resources such as training and documentation. The following is a summary of key enhancements to OpenROAD in 2023:

• Ease-of-use, fast installation and setup to run the flow.
  • Significant improvements have been made to the installation process and our enhanced documentation for multiple hardware setup options.
  • Precision Innovations makes pre-built binaries available based on nightly builds that users can directly use without the need to build locally.
• A real-time dashboard is available to customize and track key metrics for design quality: https://dashboard.theopenroadproject.org
• New PDK enablement in ORFS.
  • HEP has added support for a public PDK for IHP to support their 130nm process technology, as part of the above-mentioned government-backed initiative for Trusted Microelectronics development based on OpenROAD and other open-source tools.
  • OpenROAD now supports a private PDK from SCL. This PDK will foster research, education, and the growth of a future semiconductor ecosystem in India. Such a technology base is important to regional semiconductor economies that depend on trusted microelectronics and a resilient supply chain using their own foundries.

Key Functionality Updates

The following are some highlights of features and fixes to OpenROAD and OpenROAD-flow-scripts aimed at improving design flow efficiency and accuracy.

• Standard-cell placement and resizing now supports multi-height cells and hybrid rows
• Support for vector-based power consumption calculation
• Numerous improvements to the IO pin placer
  • Mirroring constraints
  • Simulated annealing solver for highly constrained designs
• Resizer improvements in multiple areas
  • Vt swapping
  • Gate cloning
  • Pin swapping
  • Power recovery
• Support for post-global-routing timing repair with incremental global routing
• Improved timing-aware global routing, with updating of net priorities during global routing to account for detouring
• Support for placement regions in global placement
• GUI rendering allows for interrupting to improve responsiveness
• Improved CTS obstacle avoidance and usability
• OpenROAD: 1,019 PRs merged;  315 issues closed
• OpenROAD-flow-scripts: 487 PRs merged; 112 issues closed
• OpenROAD has now had more than 20,000 commits!

What’s Ahead?

OpenROAD continues to support more silicon deployments and to make the tool and flow robust and ready for industry applications. This has been well-supported by Precision Innovations for our early adopters. The OpenROAD Initiative was launched in 2023 with the goal of further democratizing chip design through active engagement with industry and academia. This non-profit foundation’s initial focus is to broadly support and foster education and workforce initiatives for EDA and semiconductor design.

Our roadmap includes improving the accuracy of advanced analysis (timing, noise, crosstalk). Notably, addition of CCS model support is in progress. For design creation, clock tree synthesis is being enhanced to support more complex design structures with improved usability and optimization QoR. The project team also plans to broaden support for routing capabilities to support advanced nodes <12nm. Finally, OpenROAD is entering the realm of ML and GenAI: a chat assistant and the use of ML-based analysis (IR drop, detailed routing, etc.) are being developed.

So stay tuned and connected! Please get involved and reach out if you are interested in advancing the OpenROAD tool or contributing to any of the project’s initiatives:

info@precisioninno.com

https://theopenroadproject.org/contact-us/

Abacus advocates open-source usage broadly and supports a diverse ecosystem of open-source tools that serve its differentiated product portfolio by breaking barriers of cost and innovation in proprietary tools.

https://www.abacus-semi.com/affiliations.html
https://www.abacus-semi.com/FOSS.html

Abacus Semiconductor Corporation is a fabless semiconductor company that designs and engineers processors, accelerators and smart multi-homed memories for use in supercomputers and in the backend for Artificial Intelligence and Machine Learning (including Large Language Models such as ChatGPT and GPT-4) as well as traditional High Performance Compute (HPC) applications.

https://www.abacus-semi.com/index.html

It was a great opportunity for many to showcase their creativity and skills. We are glad to announce the winners : https://lnkd.in/gfUdkYbp

Problem C: https://lnkd.in/guMGRD4E . Stay tuned for more updates!