This year three OpenROAD related projects have been selected by the GSoC Initiative.
These were proposed by OpenROAD through the UCROSS/OSRE mentor organization: https://cross.ucsc.edu/news/news/20220531osre.html
Two of these projects are aimed at enhancing OpenLane documentation and thereby improving the overall user experience with installation, flow, debugging and visualization during key stages of the OpenLane design flow. A set of tutorials will be developed to enable users to quickly and easily learn both basic flow capabilities and important features such as timing optimization. The documentation will simplify installation and enhance OpenLane quick start and user guide. There are also plans to enhance the reference section of the current documentation.
The third project aims at enhancing the functionality and performance of the power planning tool in the OpenROAD flow- pdngen. Specifically, this project aims to implement the existing padring insertion code (pad.tcl) module of OpenROAD and recode the functionality in C++ for better performance and efficiency. A key objective is to ensure that designs created are of good quality for pad placement, pad filler insertion and signal routing.
These projects are ably mentored by senior project team members of OpenROAD and Efabless. The contributors to this project are familiar with OpenLane and the basic aspects of VLSI design flow.
We thank OSRE and Google/GSoC for their support and sponsorship of these important projects and look forward to a successful summer session with our interns!