TitlePublication DetailsFile
An Effective Cost-Skew Tradeoff Heuristic for VLSI Global RoutingKahng, A.B., Thumathy, S. and Woo, M., 2023, April. An Effective Cost-Skew Tradeoff Heuristic for VLSI Global Routing. In 2023 24th International Symposium on Quality Electronic Design (ISQED) (pp. 1-8). IEEE.Papers(.pdf)
Architecture exploration and VLSI design of multi-symbol arithmetic encoders for the AV1 coding formatBitencourt, T.P., 2023. Architecture exploration and VLSI design of multi-symbol arithmetic encoders for the AV1 coding format.Papers(.pdf)
Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization. ACM Transactions on Design Automation of Electronic Systems.Zheng, S., Geng, H., Bai, C., Yu, B. and Wong, M.D., 2023. Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization. ACM Transactions on Design Automation of Electronic Systems.Papers
REMOTune
Robust Physical Design and Design Technology Co-Optimization Methodologies at Advanced
VLSI Technology
Kim, M., 2023. Robust Physical Design and Design Technology Co-Optimization Methodologies at Advanced VLSI Technology (Doctoral dissertation, University of California, San Diego).Papers(.pdf)
Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix ExponentialStoikos, P., Floros, G., Garyfallou, D., Evmorfopoulos, N. and Stamoulis, G., 2023, July. Electromigration Stress Analysis with Rational Krylov-based Approximation of Matrix Exponential. In 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) (pp. 1-4). IEEE.Papers(.pdf)
A Fast Semi-Analytical Approach for Transient Electromigration
Analysis of Interconnect Trees using Matrix Exponential
Stoikos, P., Floros, G., Garyfallou, D., Evmorfopoulos, N. and Stamoulis, G., 2023, January. A fast semi-analytical approach for transient electromigration analysis of interconnect trees using matrix exponential. In Proceedings of the 28th Asia and South Pacific Design Automation Conference (pp. 1-6).Papers(.pdf)
Linear Time Electromigration Analysis Based on Physics-Informed Sparse RegressionChen, L., Jin, W., Kavousi, M., Lamichhane, S. and Tan, S.X.D., 2023. Linear Time Electromigration Analysis based on Physics-informed Sparse Regression. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.Papers(.pdf)
A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations.Zhu, Y., Wang, X., Yin, G., Zhang, Y., Luan, Z., Wang, M., Guo, P., Wan, X., Hu, S., Zhang, D. and Yang, Q., GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations.Papers(.pdf)
DREAMPlace 4.0: Timing-driven Placement with
Momentum-based Net Weighting and
Lagrangian-based Refinement
Liao, P., Guo, D., Guo, Z., Liu, S., Lin, Y. and Yu, B., 2023. DREAMPlace 4.0: Timing-driven Placement with Momentum-based Net Weighting and Lagrangian-based Refinement. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.Papers(.pdf)
OpenDRC: An Efficient Open-Source Design Rule Checking
Engine with Hierarchical GPU Acceleration
He, Z., Zuo, Y., Jiang, J., Zheng, H., Ma, Y. and Yu, B., OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration.Papers(.pdf)
An End-to-End Open-Source Linux-capable RISC-V SoC in 130nm CMOS.Benz, T., Scheffler, P., Schönleber, J. and Benini, L., Iguana: An End-to-End Open-Source Linux-capable RISC-V SoC in 130nm CMOS.Papers(.pdf)
A hierarchical automatic macro placer for large-scale complex IP blocks. arXiv preprint arXiv:2304.11761Kahng, A.B., Varadarajan, R. and Wang, Z., 2023. Hier-RTLMP: A hierarchical automatic macro placer for large-scale complex IP blocks. arXiv preprint arXiv:2304.11761.Papers(.pdf)
Low-Noise Amplifier Design: An Open-Source PerspectiveKumar, A. and Jhariya, D.K., 2023, April. Low-Noise Amplifier Design: An Open-Source Perspective. In 2023 2nd International Conference on Paradigm Shifts in Communications Embedded Systems, Machine Learning and Signal Processing (PCEMS) (pp. 1-6). IEEE.Papers(.pdf)
Assessment of Reinforcement Learning for Macro PlacementCheng, C.K., Kahng, A.B., Kundu, S., Wang, Y. and Wang, Z., 2023, March. Assessment of Reinforcement Learning for Macro Placement. In Proceedings of the 2023 International Symposium on Physical Design (pp. 158-166).Papers(.pdf)
RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell LegalizationLee, S.Y., Park, S., Kim, D., Kim, M., Le, T.P. and Kang, S., 2023, April. RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell Legalization. In 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 1-6). IEEE.Papers(.pdf)
Hardware Obfuscation Based Watermarking Technique for IPR Ownership IdentificationBagul, P. and Inamdar, V., 2023. Hardware Obfuscation Based Watermarking Technique for IPR Ownership Identification. International Journal of Reconfigurable Computing, 2023.Papers(.pdf)
Revisiting Obfuscation Metrics for Trusted
Fabrication of Designs
Nigussie, T., Revisiting Obfuscation Metrics for Trusted Fabrication of Designs.Papers(.pdf)
Open-Source IC Design for Post-Quantum CryptographyDemirs, A., Huynh, B. and Wong, M., 2023. Open-Source IC Design for Post-Quantum Cryptography.Papers(.pdf)
K-SpecPart: Supervised embedding algorithms and cut overlay for improved hypergraph partitioningBustany, I., Kahng, A.B., Koutis, I., Pramanik, B. and Wang, Z., 2023. K-SpecPart: A Supervised Spectral Framework for Multi-Way Hypergraph Partitioning Solution Improvement. arXiv preprint arXiv:2305.06167.Papers
An Open-Source 4×8 Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design FlowChen, P.H., Tsao, C. and Raina, P., 2023, May. An Open-Source $4\times 8$ Coarse-Grained Reconfigurable Array Using SkyWater 130 nm Technology and Agile Hardware Design Flow. In 2023 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1-5). IEEE.Papers
OpenSpike: An OpenRAM SNN AcceleratorModaresi, F., Guthaus, M. and Eshraghian, J.K., 2023. OpenSpike: An OpenRAM SNN Accelerator. arXiv preprint arXiv:2302.01015.Papers(.pdf)
Analysis of Digital and Embedded
Engineering Methods for System on Chip
Design
Emil, J.T., 2023. Analýza metod digitálního návrhu a softwarového vývoje systémů na čipu (Master's thesis, České vysoké učení technické v Praze. Vypočetní a informační centrum.).Papers(.pdf)
A Systematic Framework for Design-Technology Path finding with Improved Design EnablementChoi, S., Jung, J., Kahng, A.B., Kim, M., Park, C.H., Pramanik, B. and Yoon, D., 2023. PROBE3. 0: A Systematic Framework for Design-Technology Pathfinding with Improved Design Enablement. arXiv preprint arXiv:2304.13215.Papers(.pdf)
Design and Implementation of Integrated Circuits Using Open Source Tools and SKY130 Free PDKHerman, K., Montanares, M. and Marin, J., 2023, June. Design and Implementation of Integrated Circuits Using Open Source Tools and SKY130 Free PDK. In 2023 30th International Conference on Mixed Design of Integrated Circuits and System (MIXDES) (pp. 105-110). IEEE.Papers(.pdf)
AGD: A Learning-based Optimization Framework for EDA and its Application to Gate SizingPham, P. and Chung, J., 2023, July. AGD: a learning-based optimization framework for EDA and its application to gate sizing. In 2023 60th ACM/IEEE Design Automation Conference (DAC) (pp. 1-6). IEEE.Papers(.pdf)
An Energy-efficient and Accuracy-adjustable bfloat16 MultiplierPilipović, R., Bulić, P. and Lotrič, U., 2023. An Energy-efficient and Accuracy-adjustable bfloat16 Multiplier. Informacije MIDEM, 53(2), pp.79-86.Papers(.pdf)
Special Session: Machine Learning for Embedded System DesignAlcorta, E.S., Gerstlauer, A., Deng, C., Sun, Q., Zhang, Z., Xu, C., Wills, L.W., Lopera, D.S., Ecker, W., Garg, S. and Hu, J., 2023. Special Session: Machine Learning for Embedded System Design.Papers(.pdf)
An Efficient Security Closure Methodology for EM-based Attacks on Power Grid StructuresTakou, A., Stoikos, P., Moysis, M., Floros, G., Evmorfopoulos, N. and Stamoulis, G., 2023, October. An Efficient Security Closure Methodology for EM-based Attacks on Power Grid Structures. In 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (pp. 1-4). IEEE Computer Society.Papers(.pdf)
Invited Paper: IEEE CEDA DATC Emerging
Foundations in IC Physical Design and MLCAD
Research
Jung, J., Kahng, A.B., Kundu, S., Wang, Z. and Yoon, D., IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research.Papers(.pdf)
An Open-Source Constraints-Driven General Partitioning
Multi-Tool for VLSI Physical Design
Bustany, I., Gasparyan, G., Kahng, A.B., Koutis, I., Pramanik, B. and Wang, Z., 2023. An Open-Source Constraints-Driven General Partitioning Multi-Tool for VLSI Physical Design. In Proc. ICCAD.Papers(.pdf)
A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed RouteChhabria, V.A., Jiang, W., Kahng, A.B. and Sapatnekar, S.S., 2023. A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route. ACM Transactions on Design Automation of Electronic Systems.Papers
Invited Paper: Heterogeneous Acceleration for
Design Rule Checking
He, Z. and Yu, B., 2023. Heterogeneous Acceleration for Design Rule Checking.Papers
NSF Integrated Circuit Research, Education and Workforce Development Workshop Final ReportGuthaus, M., Batten, C., Brunvand, E., Gaillardon, P.E., Manohar, R., Mazumder, P., Pileggi, L. and Stine, J., 2023. NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report. arXiv preprint arXiv:2311.02055.Papers
Toward Reinforcement Learning-based Rectilinear Macro Placement Under Human ConstraintsLe, T.P., Nguyen, H.T., Baek, S., Kim, T., Lee, J., Kim, S., Kim, H., Jung, M., Kim, D., Lee, S. and Choi, D., 2023. Toward Reinforcement Learning-based Rectilinear Macro Placement Under Human Constraints. arXiv preprint arXiv:2311.03383.Papers
A Framework for Graph Learning and Augmentation on RTL DesignsLi, Y., Liu, M., Mishchenko, A. and Yu, C., 2023. Verilog-to-PyG--A Framework for Graph Learning and Augmentation on RTL Designs. arXiv preprint arXiv:2311.05722.Papers(pdf)
Invited Paper: Accelerating Routability and Timing
Optimization with Open-Source AI4EDA Dataset
CircuitNet and Heterogeneous Platforms
Jiang, X., Guo, Z., Chai, Z., Zhao, Y., Lin, Y., Wang, R. and Huang, R., Accelerating Routability and Timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms.Papers (pdf)
Netlist Whisperer: AI and NLP Fight Circuit Leakage!Nair, M., Sadhukhan, R., Pearce, H., Mukhopadhyay, D. and Karri, R., 2023, November. Netlist Whisperer: AI and NLP Fight Circuit Leakage!. In Proceedings of the 2023 Workshop on Attacks and Solutions in Hardware Security (pp. 83-92).Papers